Demand for SiC substrates is growing as the demand for SiC-based power and RF devices increases. The physical properties of SiC result in better thermal conductivity, higher breakdown voltage, higher switching performance and lower resistivity than silicon devices resulting in thinner, lighter, and more cost-effective devices. Yet the adoption of SiC is slowed by cost and by the difficulty of processing the material. Revasum’s wire-sawn SiC grinding and CMP process reduces costs, enabling wide-spread adoption of SiC substrates.
Revasum’s 7AF-HMG combines hardware and software improvements with optimized wheels to achieve better grind performance at a lower cost per wafer. , Individual wafer processing results in better wafer-to- wafer consistency more accurate thickness targeting within ±3µm and total thickness variation (TTV) between 1 to 3µm with typical wire sawn samples, . In addition, the wafer can be shaped to accommodate for center-slow or center-fast polishing processes, which helps maintain post CMP TTV.
The 6DS-SP is a two-table, two-head CMP system ideally suited to this two-step SiC process. Revasum’s ViPRR-XR carrier, which is advanced compared to batch polishers, is simpler than membrane carriers used for state-of-the-art IC manufacturing, and better at maintaining post grind TTV. Higher downforce, in-situ pad conditioning and increased spindle RPM enable faster removal rate.